/* Verilog model created from schematic buffer.sch -- Nov 21, 2012 15:31 */

module buffer( clear, clk, enable, i, o );
 input clear;
 input clk;
 input enable;
 input [11:0] i;
output [11:0] o;



FD1P3IX I9 ( .CD(clear), .CK(clk), .D(i[11]), .Q(o[11]), .SP(enable) );
FD1P3IX I10 ( .CD(clear), .CK(clk), .D(i[10]), .Q(o[10]), .SP(enable) );
FD1P3IX I11 ( .CD(clear), .CK(clk), .D(i[9]), .Q(o[9]), .SP(enable) );
FD1P3IX I12 ( .CD(clear), .CK(clk), .D(i[8]), .Q(o[8]), .SP(enable) );
FD1P3IX I1 ( .CD(clear), .CK(clk), .D(i[7]), .Q(o[7]), .SP(enable) );
FD1P3IX I2 ( .CD(clear), .CK(clk), .D(i[6]), .Q(o[6]), .SP(enable) );
FD1P3IX I3 ( .CD(clear), .CK(clk), .D(i[5]), .Q(o[5]), .SP(enable) );
FD1P3IX I4 ( .CD(clear), .CK(clk), .D(i[0]), .Q(o[0]), .SP(enable) );
FD1P3IX I5 ( .CD(clear), .CK(clk), .D(i[1]), .Q(o[1]), .SP(enable) );
FD1P3IX I6 ( .CD(clear), .CK(clk), .D(i[2]), .Q(o[2]), .SP(enable) );
FD1P3IX I7 ( .CD(clear), .CK(clk), .D(i[3]), .Q(o[3]), .SP(enable) );
FD1P3IX I8 ( .CD(clear), .CK(clk), .D(i[4]), .Q(o[4]), .SP(enable) );

endmodule // buffer
